The present invention relates to display driving apparatus and display apparatus module that are capable of suppressing the circuit scale and reducing the power consumption of the circuit.
FIG. 9 is a block diagram showing a liquid crystal display apparatus of a TFT (Thin-Film Transistor) type that is a typical one of active matrix types.
The liquid crystal display apparatus is provided with a liquid crystal display section and a liquid crystal display apparatus (liquid crystal driving circuit) that drives the liquid crystal display section. The liquid crystal display section is provided with a liquid crystal panel 901 of TFT-type. The liquid crystal panel 901 is provided with a plurality of display unit elements (pixels) that are disposed in a matrix manner and an opposite electrode (common electrode) 906.
In the mean time, the liquid crystal driving apparatus is provided with source driver 902 and gate driver 903 each of the drivers including an IC (Integrated Circuit) chip, a controller 904, and a liquid crystal driving power source 905.
The source driver 902 and the gate driver 903 are provided as follows, in general. More specifically, by providing, on ITO (Indium Tin Oxide) terminals that are provided so as to extend from the inside of the liquid crystal panel 901 toward its peripheral part, such as a TCP (Tape Carrier Package) that is realized by mounting the IC chip on a film which has been subjected to a predetermined wiring, and combining, or providing the IC chip directly to the ITO terminals of the liquid crystal panel 901 via an ACF (Anisotropic Conductive Film) by means of thermal bonding, and combining, the drivers are provided.
In order to further miniaturize the liquid crystal display apparatus, the controller 904, the liquid driving power source 905, the source driver 902, and the gate driver 903 are combined so as to have 1-chip structure, or 2-chip structure, or 3-chip structure. FIG. 9 shows these structures separately for respective functions.
The controller 904 outputs to the source driver 902 (a) the digitized display data (for example, RGB image signals corresponding to red, green, and blue, respectively) indicated as D in FIG. 9 and (b) respective control signals indicated as S1 in FIG. 9. The controller 904 also outputs respective control signals indicated as S2 in FIG. 9 to the gate driver 903. The source driver 902 mainly receives the control signals such as a horizontal synchronizing signal (a latch signal Ls), a start pulse signal, and a clock signal for source driver-use. The gate driver 903 mainly receives the control signals such as a vertical synchronizing signal and a clock signal for gate driver-use. Note that a power source that drives the respective IC chips (gate driver IC and source driver IC) is omitted in FIG. 9.
The liquid crystal driving power source 905 supplies the source driver 902 and the gate driver 903 with a voltage for liquid crystal panel display-use (a reference voltage for generating a voltage for gradation display-use).
The display data that have been externally inputted are sent to the source driver 902 via the controller 904 as the display data D that are a digital signal. The source driver 902 carries out the sampling with respect to the inputted display data D in a timexe2x80x94sharing manner and store the sampling result, and then carry out the D/A conversion in which the display data D is converted into the voltage for gradation displayxe2x80x94use so as to be in synchronization with the horizontal synchronizing signal (may be referred to as a latch signal Ls).
The source driver 902 sends the analog voltage for gradation display-use (the voltage for gradation display-use) that is a resultant of the D/A conversion to an associated source signal line 1004 (see FIG. 10) provided in the liquid crystal panel 901 via the liquid crystal driving voltage output terminal.
The following description deals with the structure of the liquid crystal panel 901 with reference to FIG. 10. The liquid crystal panel 901 is provided with pixel electrodes 1001, pixel capacitor 1002, TFTs 1003 acting as switching device that carry out ON/OFF the voltages applied to the respective pixels, source lines 1004, gate signal lines 1005, and an opposite electrode 1006 of the liquid crystal panel (corresponding to the opposite electrode 906 shown in FIG. 9). Note that the area indicated as xe2x80x9cAxe2x80x9d corresponds to a single pixel in FIG. 10.
The voltage for gradation display-use having the amplitude that varies depending on the brightness displayed in each target pixel is supplied to the source line 1004 from the source driver 902 shown in FIG. 9. Scanning signals are applied to the respective gate signal lines 1005 from the gate driver 903 shown in FIG. 9 so that a plurality of TFTs 1003, that are provided in a longitudinal direction (i.e., in a direction in which the source signal lines 1004 are extended) are successively turned ON.
In the case where a TFT 1003 is turned ON, when a pixel electrode 1001 connected with the drain of such a TFT 1003 receives the voltage for gradation display-use from the source signal line 1004, electric charges are stored (charged) in the pixel capacitor 1002 formed between the pixel electrode 1001 and the opposite electrode 1006. Then, when the selection by the gate signal lines 1005 is completed and the TFT 1003 changes into an OFF (non-selection) state, the voltages that have been written into the pixel capacitor 1002 are maintained. The ON/OFF operation causes the light transmittance of the respective display unit elements (pixels) to change in accordance with the level of the voltage for gradation display-use that has been written into each pixel. This allows to realizing a target gradation display.
FIGS. 11 and 12 show an example of the waveform of the liquid crystal driving voltage to be applied to the source signal line 1004, the gate signal line 1005, and the pixel electrode 1001 shown in FIG. 10, respectively. In FIGS. 11 and 12, reference numerals 1101 and 1201 show the waveform of the voltage for gradation display-use outputted from the source driver 902 to the source signal line 1004. In FIGS. 11 and 12, reference numerals 1102 and 1202 show the waveform of the scanning signal, for controlling of ON/OFF of the TFT 1003, that is outputted from the gate driver 903 to the gate signal line 1005. Note that when the reference numeral 1102 or 1202 is a high level, the TFT 1003 is in an ON state, and when a low level, the TFT 1003 is in an OFF state.
In FIGS. 11 and 12, reference numerals 1103 and 1203 show the electrical potential (voltage) of the opposite electrode 1006 (see FIG. 10), and 1104 and 1204 show the waveform of the voltage to be applied to the pixel electrode 1001. The change (see FIG. 11, for example) in the waveform of the voltage to be applied to the pixel electrode 1001 is explained by the fact that the voltage level corresponding to the electric charges charged in the pixel capacitor 1002 during the period of time in which (a) the TFT 1003 is turned ON when the scanning signal 1102 is a high level, this causes that the pixel capacitor 1002 starts to be charged (i.e., the voltage 1101 for gradation display-use is written), (b) the scanning signal is a low level so that the TFT 1003 is turned OFF, when the voltage across the pixel capacitor 1002 reaches a predetermined voltage level, and (c) thereafter, the scanning signal becomes a high level again. Note that the similar description is made with respect to the voltage of the waveform indicated as the reference numeral 1204 shown in FIG. 12.
Note that the voltage to be applied to the liquid crystal material (not shown) is equal to the difference of electric potentials (voltage difference) between the pixel electrode 1001 and the opposite electrode 1006 (see the oblique lines shown in FIGS. 11 and 12).
In FIGS. 11 and 12, the amplitudes of the respective voltages 1101 and 1201 for gradation display-use to be applied to the source signal line 1004 are different from each other. This allows to carrying out the display so as to have respective different gradations. In other words, the amplitude of the voltage for gradation display-use is changed so that the voltage differences (see the oblique lines shown in FIGS. 11 and 12) between the pixel electrode 1001 and the opposite electrode 1006 are different from each other, thereby realizing a target gradation display. Note that the number of the gradations that can be displayed is determined in accordance with the number of the possible selections of the voltages to be applied to the liquid crystal material, i.e., in accordance with the number of selections of the amplitudes of the voltages for gradation-use outputted as the analog signal.
By the way, the present invention relates to an output circuit in a circuit for gradation display-use that occupies especially great circuit scale and power consumption. Accordingly, the following description deals with the liquid crystal driving apparatus mainly focusing on the source driver 902.
FIG. 13 shows a block structure of the source driver 902. The following description deals with its basic parts with reference to FIG. 13. Digital display data DR, DG, and DB (for example, each being 6-bit data) that are respectively transmitted from the controller 904 (see FIG. 9) are once latched by an input latch circuit 1301. Note that the Digital display data DR, DG, and DB correspond to red, green, and blue data, respectively, and have been referred to as the display data D in FIG. 9.
A start pulse SP and a clock signal CK for source driver-use are supplied to the source driver 902 from the controller 904. The start pulse SP is successively transmitted through the respective stages in the shift register in synchronization with the clock signal CK. This causes that (1) each stage of the shift register circuit 1302 outputs an output signal to a sampling memory circuit 1303 and (2) the final stage of the shift register circuit 1302 outputs a start pulse signal SP (a cascade output signal S) for source driver-use to the source driver of the next stage.
In synchronization with the output signal outputted from each stage of the shift register circuit 1302 to a sampling memory circuit 1303, the digital display data DR, DG, and DB that have been latched by the input latch circuit 1301 are once stored by the sampling memory circuit 1303 in a time-sharing manner and are outputted to the next hold memory circuit 1304.
More concretely, when the digital display data DR, DG, and DB corresponding to one horizontal synchronizing signal (see FIG. 14) are stored by the sampling memory circuit 1303, the hold memory circuit 1304 fetches the output signals from the respective stages of the sampling memory circuit 1303 in accordance with the horizontal synchronizing signal (the latch signal Ls) that is supplied from the controller 904 (see FIG. 9) so as to output the output signal thus fetched to a level shifter circuit 1305 of the next stage. Simultaneously, the hold memory circuit 1304 maintains the digital display data DR, DG, and DB until the next horizontal synchronizing signal is supplied. Along with the outputting operation, the hold memory circuit 1304 maintains the digital display data DR, DG, and DB until the next horizontal synchronizing signal is inputted.
The level shifter circuit 1305 is provided for converting and outputting the input signal by such as boosting (increasing) the input signal so as to be suited to the D/A converter circuit 1306 of the next stage that proceeds the voltage to be applied to the liquid crystal panel 901 (see FIG. 9). A reference voltage generation circuit 1309 generates a variety of analog voltages for gradation display-use in accordance with a reference voltage VR outputted from a liquid crystal driving power source 905 (see FIG. 9) and sends them to the D/A converter circuit 1306.
The D/A converter circuit 1306 selects an analog voltage, among the variety of analog voltages supplied from the reference voltage generation circuit 1309, in accordance with the digital display data that have been subjected to the level conversion by the level shifter circuit 1305. The analog voltage showing the gradation display is outputted to the respective source signal lines 1004 of the liquid crystal panel 901 from the respective output terminals 1308 for liquid crystal driving voltages (hereinafter referred to as the output terminals, merely) via the output circuit 1307. The output circuit 1307 acts as a buffer circuit, and is realized by a voltage follower circuit adopting such as differential amplifier circuits.
Note that FIGS. 14, 15(a), and 15(b) show timing charts of the input signal or the output signal of the source driver 902 and the gate driver 903 (see FIG. 9) which have been described with reference to FIGS. 9 through 13. As shown in FIG. 14, (a) the vertical synchronizing signal which is inputted to the gate driver 903 from the controller 904 and (b) the horizontal synchronizing signal (the latch signal Ls) which is inputted to the source driver 902 are outputted so as to have a predetermined relation between them. Further, the scanning signals of the respective gate signal lines G1 through Gn of the gate driver 903 (corresponding to the gate signal line 1005 shown in FIG. 10) successively outputs selection pulse (a voltage signal of High level shown in FIG. 12) in synchronization with the horizontal synchronizing signal once a vertical synchronizing period.
In contrast, as has been described earlier, the scanning signal, the clock signal CK for source driverxe2x80x94use, the start pulse signal SP, the digital display data DR, DG, DB (referred to as the display data signal in the drawing), and the horizontal synchronizing signal have the relation among their waveforms shown in FIG. 15(a). The signal waveform (the source driver output in the drawing) to be outputted to the respective source signal lines 1004 from the output terminals 1308 of the source driver 902 has the relation shown in FIG. 15(b). Note that FIGS. 15(a) and 15(b) show an example in which the output terminals 1308 of the source driver 902 are constituted by totally 300 terminals, i.e., X1 through X100, Y1 through Y100, and Z1 through Z100 (100 output terminals for colors R, G, and B, respectively). This ensures to cope with 64 gradation displays as follows.
Here, the following description deals with the circuit configuration of the reference voltage generation circuit 1309, the D/A converter circuit 1306, and the output circuit 1307 in detail with mainly reference to FIGS. 13, 16, 17, and 18.
FIG. 16 shows an example of the circuit configuration of the reference voltage generation circuit 1309. When the digital display data DR, DG, and DB for respective colors R, G, and B are constituted by 6 bits, respectively, the reference voltage generation circuit 1309 outputs 64 types of analog voltages that correspond to 64 (=26) gradation displays. The following description deals with its concrete circuit configuration.
The reference voltage generation circuit 1309 is realized by the simplest configuration of a resistor division circuit in which resistors R0 through R7 are connected with each other in a series manner. Each of the resistors R0 through R7 is realized by eight resistors that are connected with each other in series. For example, as to the resistor R0, as shown in FIG. 17, eight resistors R01, R02, . . . , R07, R08 are connected in series with each other, thus the resistor R0 is realized. The other resistors R1 through R7 are realized by the configuration similar to the resistor R0. Thus, the reference voltage generation circuit 1309 is realized by totally 64 resistors that are connected in series with each other. Note that each of the resistors R0 through R7 are determined by considering such as the gamma (xcex3) correction.
The reference voltage generation circuit 1309 is provided with nine (9) half tone voltage input terminals corresponding to nine reference voltages Vxe2x80x20, Vxe2x80x28, . . . , Vxe2x80x256, Vxe2x80x264. The half tone voltage input terminal corresponding to the reference voltage Vxe2x80x264 is connected with one end of the resistor R0. The half tone voltage input terminal corresponding to the reference voltage Vxe2x80x256 is connected with the other end (i.e., the connection point connecting the resist R0 and the resistor R1). The connection points of the respective neighboring resistors R1 and R2, R2 and R3, . . . , and, R6 and R7 are connected with the half tone voltage input terminals corresponding to the reference voltages Vxe2x80x248, Vxe2x80x240, . . . , Vxe2x80x28, respectively. One end of the resistor R7 whose other end is connected with the resistor R6 is connected with the half tone voltage input terminal corresponding to the reference voltage Vxe2x80x20.
With the circuit configuration, it is possible to obtain the voltages V1 through V63 from the connection points connecting the respective two neighboring resistors of the 64 resistors. Thus, the voltages V1 through V63 and the voltage V0 provide totally 64 kinds of analog voltages (V0 through V63) for gradation display-use. Namely, when the reference voltage generation circuit 1309 is realized by the resistor division circuit, the analog voltages V0 through V63 for gradation displayxe2x80x94use are determined in accordance with the ratios of the 64 resistors. The 64 analog voltages V0 through V63 are sent to the D/A converter circuit 1306 from reference voltage generation circuit 1309.
Note that the reference voltages Vxe2x80x20 and Vxe2x80x264 of both ends are always applied to the half tone voltage input terminals in general, while seven half tone voltage input terminals corresponding to the reference voltages Vxe2x80x28 through Vxe2x80x256 are used for fine adjustment. In actual, there are some cases where no voltages are applied to such seven half tone voltage input terminals.
The following description deals with the D/A converter circuit 1306. FIG. 18 shows an example of the circuit configuration of the D/A converter circuit 1306. Note that the circuit configuration (voltage follower circuit) of the output circuit 1307 is also shown in FIG. 18.
In the D/A converter circuit 1306, a MOS transistor or a transmission gate is provided as each analog switch (hereinafter referred to as a switch) so that one of the inputted 64 analog voltages V0 through V63 is selected in accordance with the display data made of the 6-bit digital signal. More specifically, the switch is turned ON or OFF in accordance with each bit (Bit0 through Bit5) of the display data made of 6-bit digital signal. This allows one of the inputted 64 analog voltages to be selected and outputted to the output circuit 1307. The following description deals with the selection and outputting.
In the 6-bit digital signal, the Bit0 indicates an LSB (the Least Significant Bit) and the Bit 5 indicates an MSB (the Most Significant Bit). The switches are arranged so that two switches form one pair. 32 pairs of switches (64 switches) are provided for (correspond to) the Bit0. 16 pairs of switches (32 switches) are provided for the Bit1. The number of the switches is reduced to be half for each Bit. Finally, a pair of switches (2 switches) is provided for the Bit5. Namely, 63 (=25+24+23+22+21+1) pairs of switches (126 switches) are totally provided.
One end of the switches corresponding to Bit0 acts as an input terminal for the foregoing respective voltages V0 through V63. The other ends of the respective two switches are connected with each other, and are further connected with one end of the switches corresponding to Bit1. Thereafter, these connecting arrangements are repeated up to the switches corresponding to Bit5. Finally, one electric line is drawn from the switches corresponding to Bit5 so that it is connected with the output circuit 1307.
It is assumed that the switches corresponding to Bit0 through Bit5 are referred to as switch groups SW0 through SW5. Each switch of the switch groups SW0 through SW5 is controlled in accordance with the 6-bit digital display data (Bit0 through Bit5) as follows.
In the switch groups SW0 through SW5, when the corresponding Bit is xe2x80x9c0xe2x80x9d (Low level), one (corresponding to the lower switch in the drawing) of the two analog switches that form a pair is turned ON. In contrast, when the corresponding Bit is xe2x80x9c1xe2x80x9d (High level), the other (corresponding to the upper switch in the drawing) of the two analog switches is turned ON. In the drawing, the Bit0 through Bit5 show (111111), the upper switches are turned ON and the lower switches are turned OFF in all switch pairs In this case, the voltages V63 is sent to the output circuit 1307 from the D/A converter circuit 1306.
Similarly, for example, when the Bit0 through Bit5 show (111110), the voltages V62 is sent to the output circuit 1307 from the D/A converter circuit 1306. When the Bit0 through Bit5 show (000001), the voltages V1 is sent to the output circuit 1307 from the D/A converter circuit 1306, and when the Bit0 through Bit5 show (000000), the voltages V0 is sent to the output circuit 1307 from the D/A converter circuit 1306. Thus, one of the analog voltages (V0 through V63) for gradation display-use is selectively outputted in accordance with the digital display so as to realize the gradation display.
In general, the number of the reference voltage generation circuit 1309 in a single source driver IC is one so as to be shared. In contrast, the numbers of the D/A converter circuit 1306 and the output circuit 1307 are respectively one so as to correspond to the respective output terminals 1308 (see FIG. 13).
In the case of the color display, since the output terminals 1308 are used in accordance with the respective colors, the numbers of the D/A converter circuit 1306 and the output circuit 1307 that are used are respectively one for every pixel and for every color. More specifically, when the number of the pixels along the length of the liquid crystal panel 901 is N and the output terminals 1308 for respective red, green, and blue colors are indicated by R, G, and B with suffixes n (n=1, 2, . . . , N), the output terminals 1308 are indicated as R1, G1, B1, R2, G2, B2, . . . , RN, GN, BN. Therefore, the numbers of the required D/A converter circuits 1306 and output circuits 1307 are 3N, respectively.
The following description deals with a variety of circuit configurations of the reference voltage generation circuit 1309, the D/A converter circuit 1306, and the output circuit 1307 with reference to FIGS. 19 through 21.
The circuit configuration shown in FIG. 19 includes the circuit configurations shown in FIGS. 16 and 17. The D/A converter circuit 1306 to which the voltages V0 through V63 for gradation display are inputted via the reference voltage generation circuit 1309 selects a voltage for gradation display-use in accordance with the inputted digital display data (an output signal of the level shifter circuit) and outputs the selected voltage to the output circuit 1307.
The output signal of the D/A converter circuit 1306 is sent to the source signal line 1004 in the liquid crystal panel via the output circuit 1307 that acts as a buffer circuit and the output terminal 1308, successively. Note that the reference numeral 1008 in FIG. 19 shows a model of a single pixel in the liquid crystal panel and the wiring capacitance of a source signal line 1004 that is connected with the pixel. Note that the reference numeral 1002 indicates the pixel capacitor, the reference numeral 1003 indicates the TFT, the reference numeral 1006 indicates the electric potential of the opposite electrode, and the reference numeral 1007 indicates the wiring capacitor of the source signal line 1004.
As mentioned above, the circuit configuration shown in FIG. 19, (a) obtains the voltages V0 through V63 which are different from each other from the resistor division circuit in which a plurality of resistors are connected in series with each other, (b) selects a voltage among the voltages V0 through V63 which corresponds to the digital display data, and (c) outputs via the output circuit 1307 that acts as a buffer circuit the selected voltage that has been subjected to the low impedance so as to charge the wiring capacitance 1007 of the source signal line 1004 and the pixel capacitor 1002 in the liquid crystal panel.
As shown in FIG. 20, it may be possible to remove the output circuit 1307 from the circuit configuration of FIG. 19. In this case, the circuit configuration (a) obtains the voltages V0 through V63 which are different from each other from the resistor division circuit in which a plurality of resistors are connected in series with each other, (b) selects a voltage among the voltages V0 through V63 which corresponds to the digital display data, and (c) outputs the selected voltage as it is to the source signal line 1004 so as to charge the wiring capacitance 1007 and the pixel capacitor 1002.
As shown in FIG. 21, it may be arranged so that buffer circuits 1310 which correspond to the output circuit 1307 are electrically connected with the reference voltage generation circuit 1309 and the D/A converter circuit 1306, i.e., it may be arranged so that the voltages V0 through V63 are sent to the D/A converter circuit 1306 via respective buffer circuits 1310 that correspond to the output circuit 1307. In this case, the voltages V0 through V63 are subjected to the low impedance by the respective buffer circuits 1310 and are sent to the D/A converter circuit 1306, and then one of the voltages that corresponds to the digital display data is selected by the analog switches so that the wiring capacitance 1007 and the pixel capacitor 1002 are charged.
In the market of the liquid crystal display apparatus, it is foreseen that (a) the large size of the screen due to the enlargement of the usage of the monitor of the liquid crystal display apparatus and (b) the increase of the pixels due to the high precision rapidly develop. This causes, in especial, each source driver 902 which has many output terminals for liquid crystal driving voltages to be subjected to having further many output terminals. Furthermore, with acceleration, the low cost and the lightweight of the liquid crystal display apparatus cause a single source driver 902 to be subjected to having many outputs of the output terminals for liquid crystal driving voltages (having further many output terminals). For example, it is likely that 1000 output terminals are required (300 output terminals were required for the conventional art).
When coping with the further many output terminals, the circuit configuration of the source driver 902 shown in FIG. 13, in which a low impedance output converter means (output circuit 1307) that adopts a single differential amplifier circuit (operational amplifier circuit) such as a voltage follower circuit for a single output voltage for liquid crystal driving voltage, generally needs many circuit devices of the analog circuit that constitutes the low impedance output converter means This causes the layout area to become large and the operation current for stabling the operation point to become great.
Accordingly, as the output terminals of liquid crystal driving voltages become more and more, the layout area of the output circuit 1307 of the source driver 902 becomes large and the power consumption becomes large. This causes the chip size of the entire source driver IC and the power consumption to become large, respectively.
The object of the present invention is to provide a display driving apparatus and display apparatus module that are capable of suppressing the increasing in the circuit scale (i.e., the chip size) with the increasing in the number of terminals and the increasing of the power consumption.
In order to achieve the object, a display driving apparatus, in accordance with the present invention, in which a plurality of types of driving voltages that vary depending on display data are outputted to a display section from a plurality of output terminals via a low impedance output section, and is characterized in that (a) each low impedance output section is connected with the plurality of output terminals via a switch section, and (b) the low impedance output section is shared by the plurality of output terminals in response to the switch section.
With the arrangement, a single low impedance output section is connected with a plurality of output terminals via the switch section. The switching operation of the switch section allows that the single low impedance output section is used by the plurality of output terminals. Namely, the single low impedance output section is shared by the plurality of output terminals. Accordingly, when compared with the case where low impedance output sections are provided for respective output terminals, it is possible to suppress the increasing in the circuit scale of the liquid crystal driving apparatus (i.e., the chip size of the case where the liquid crystal driving apparatus is in the form of chip) with the increasing in the number of output terminals and the increasing of the power consumption.
Further, since the low impedance output section is shared, it is possible to avoid that the display unevenness occurs due to the voltage deviation, on the output side, which is caused by the offset voltages at the input stage of differential amplifier circuits, the offset voltages being generated by the unevenness of the factors such as the manufacturing conditions in the respective differential amplifier circuits used as the low impedance output section.
A display apparatus module in accordance with the present invention is characterized by having the above display driving apparatus.
With the arrangement of the display apparatus module, it is possible to suppress the increasing in the circuit scale of the liquid crystal driving apparatus (i.e., the chip size of the case where the liquid crystal driving apparatus is in the form of chip) with the increasing in the number of output terminals and the increasing of the power consumption. Further, since the low impedance output section is shared, it is possible to avoid that the display unevenness occurs due to the voltage deviation, on the output side, which is caused by the offset voltages at the input stage of differential amplifier circuits, the offset voltages being generated by the unevenness of the factors such as the manufacturing conditions in the respective differential amplifier circuits used as the low impedance output section.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description. The present invention will become more fully understood from the detailed description given hereinafter and the accompanying drawings that are given by way of illustration only, and thus, are not limitative of the present invention.